CPU Design

VHDL programming project with FPGA Basys3 board simulating the features of a 16 bit CPU.

Date: May 2018 -> April 2018

Technologies Used: VHDL | Xilinx Vivado Software | Digilent Basys3 board with a Xilinx Artix 7 FPGA

Report: download

Code: Send me an email

Video Demonstration: Coming Soon